The Fundamental Unit of Storage Device the D-latch

in our computers the storage device is a fundamental part which is made up of resistors or logic gates. all the logic gates makeup the D-latch together and then many D-latch became resistors together which contain the data in the form of 0 and one the SI unit of data is bit and the number of 0 or 1 is decided as the one bit. a single data latch contain one bit of memory which is equal to the 0 or 1 and all the D-latch makeup together resistor which can be contain 8 bit or 16 bit or even 32bit of memory these memory can be delete with the time which is considered as the clock signal when the clock signal is high (the voltage of on) then the logic gates will allow the data to come in the locking space (the memory) and when the clock signal is low then the the data will stored in the memory until the clock signal is not turn on the data will stay stored. the data latch is the just the modified version of the set-reset latch just like the wireless earbuds is the modified version of the wired earbuds the data latch work on the a lock or loop system in which the signal will saty on or off (1 or 0) until the loop not break by another signal ( clock signal )

1 Two NOR gate ( can be make from transistors or use ICs for a smaller circuit )

2 Two AND gate ( can be make from transistor or use ICs )

3 one NOT gate for inverse signal in one AND gate

4 clock signal or can use a simple button for turn on or off

5 output signal detector like LED or multimeter or a ocilloscop

6 input switch for sending data

The single bit data latch is made of two AND and two NOR gates the AND gates gives the data and clock signal and NOR gates will trap that data in a loop which will stay 0 or 1 and data latch is also called the D flip-flop because the data latch is derived from bistable multivibrator or set-reset latch the data latch have the two output and two input one input is for data entry and another is for clock signal and one output is main data which stored and another is current data which is not need to store and pass away from the D-latch or resistor

when The AND gate's input is 0 and 1 then it's output will be 0 and another AND gate will receive the signal 1 and 1 because the NOT gate inverse the input signal in the another AND gate this two AND gate setup will give the signal 0 and 1 with the data input and clock input and then the NOR gate will take the 0 and 1 signal and remaining two wire of different NOR gate connected to their own output signal in which one is stored data and one is current data

the circuit contain the two AND gate which output is connected to one-one input of NOR gate and the another two input is connected to the output of different NOR gates this setup will close and open the data in a loop the NOT gate is connected to the remaining input wire of the both AND gate the input signal is described as the data in for of 0 and 1 the D-data latch is take the data and then low the signal of clock which will stored the signal and another output is have no storge it will not stay stored it will show the current data coming in the input signal and this full setup can see in the step1 image

The data latch will take the input, store it and then release it when need to use by ALU the signal is the following:

In This Table (show above)

1 the enable(E) is the clock signal 0 means the voltage is off and when the signal is 1 the voltage is on

2 the data(D) is stored data which is is depend on the the enable signal

3 the output (Q) if the enable is 0 then the stored data is stay unchanged if the signal is 1 then the stored data can be changed

4 the another Q is current data coming in the D-latch which don't need to store