module wam_fsm (
    input wire clk_19,
    input wire clr,
    input wire [7:0] sw,
    input wire [7:0] tap,
    input wire [7:0] holes,
    output reg [7:0] hit,
    output reg [7:0] holes_out,
    output reg [3:0] hrdn_out
);

    reg [1:0] state;
    reg [7:0] tap_reg;
    reg [7:0] holes_reg;
    reg [7:0] hit_reg;
    reg [3:0] hrdn_reg;

    // FSM states
    parameter IDLE = 2'b00;
    parameter HIT_DETECTED = 2'b01;
    parameter HIT_CONFIRMED = 2'b10;

    always @(posedge clk_19) begin
        if (clr) begin
            state <= IDLE;
            tap_reg <= 8'b0;
            holes_reg <= 8'b0;
            hit_reg <= 8'b0;
            hrdn_reg <= 4'b0;
        end
        else begin
            case (state)
                IDLE: begin
                    tap_reg <= tap;
                    holes_reg <= holes;
                    hrdn_reg <= hrdn_out;

                    if (tap_reg != 8'b0) begin
                        state <= HIT_DETECTED;
                    end
                end

                HIT_DETECTED: begin
                    if (tap_reg == 8'b0) begin
                        state <= IDLE;
                    end
                    else if (tap_reg & holes_reg != 8'b0) begin
                        state <= HIT_CONFIRMED;
                        hit_reg <= tap_reg & holes_reg;
                    end
                end

                HIT_CONFIRMED: begin
                    if (tap_reg == 8'b0) begin
                        state <= IDLE;
                    end
                    else if (hit_reg != 8'b0) begin
                        state <= HIT_CONFIRMED;
                    end
                    else begin
                        state <= HIT_DETECTED;
                    end
                end
            endcase
        end
    end

    always @(posedge clk_19) begin
        case (state)
            IDLE: begin
                holes_out <= holes_reg;
                hit <= 8'b0;
            end

            HIT_DETECTED: begin
                holes_out <= holes_reg;
                hit <= 8'b0;
            end

            HIT_CONFIRMED: begin
                holes_out <= holes_reg & ~hit_reg;
                hit <= hit_reg;
            end
        endcase
    end

endmodule