entity counter is
        Port ( CLK : in  STD_LOGIC;
               RST : in  STD_LOGIC;
               COUNT_EN : in  STD_LOGIC;
               stop_cond : out STD_LOGIC
                  );
    end counter;
    
    architecture Behavioral of counter is
    signal countIn: STD_LOGIC_VECTOR (4 downto 0); 
    begin
        process(RST, CLK)
        begin
                if RST ='1' then
                    countIn <= (others => '0');
                elsif rising_edge(clk) then
                    if countIn = "11011" then
                        CountIn <= (others => '0');
                        stop_cond <= '1'; 
                    elsif COUNT_EN = '1' and countIn /= "11011" then 
                        CountIn <= CountIn + 1;
                        stop_cond <= '0'; 
                    end if;
                
            end if;

        end process;
    
        
    end Behavioral;